bloqade_lanes_bytecode_core/isa/
mod.rs

1//! Vihaco-backed instruction set (ISA) for the Bloqade Lanes bytecode.
2//!
3//! This is the bytecode instruction set, built on the [`vihaco`] virtual-ISA
4//! framework (the migration off the original hand-rolled format), per
5//! <https://github.com/QuEraComputing/bloqade-lanes/issues/769>.
6//!
7//! The instruction set is defined once as a `#[derive(Instruction, Parse)]`
8//! enum; vihaco's derive macros then generate:
9//!
10//! - binary encode/decode ([`vihaco::instruction::WriteBytes`] /
11//!   [`vihaco::instruction::FromBytes`]) — a 1-byte opcode followed by a
12//!   little-endian payload, zero-padded to a fixed [`INSTRUCTION_WIDTH`]-byte
13//!   word, so a program is simply N concatenated words;
14//! - a text (`.sst`) parser ([`vihaco_parser_core::Parse`]).
15//!
16//! This adopts vihaco's **native** byte layout (the issue #769 decision); it is
17//! intentionally *not* compatible with the original `BLQD` container that the
18//! hand-rolled bytecode used.
19//!
20//! ## CPU ops are reused from `vihaco-cpu`
21//!
22//! Rather than re-defining stack/const opcodes, the [`Instruction::Cpu`]
23//! variant nests the entire [`vihaco_cpu::Instruction`] set (a stack machine
24//! with `const.<type>`, `dup`, `halt`, arithmetic, …), with parsing
25//! `#[delegate]`d to vihaco-cpu's own parser and printing via its `Display`.
26//! Three stack ops stay lanes-native because vihaco-cpu can't round-trip them
27//! through text:
28//!
29//! - `pop`, `swap` — vihaco-cpu has no such opcodes;
30//! - `return` — vihaco-cpu's `Return` is parser-deferred to an orchestrator
31//!   (`ret` does not parse standalone), and lanes needs a terminator that
32//!   round-trips.
33//!
34//! Consequence: CPU text syntax is now vihaco-cpu's (`const.i64 42`,
35//! `const.f64 1.5`, `dup`, `halt`), not the legacy `const_int` / `const_float`.
36
37pub mod def;
38pub mod parse_helpers;
39pub mod program;
40pub mod text;
41pub mod validate;
42
43pub use def::{INSTRUCTION_WIDTH, Instruction};
44pub use program::{LanesInfo, Program, from_code};
45pub use text::{parse_text, to_text};
bloqade_lanes_bytecode_core/isa/mod.rs

bloqade_lanes_bytecode_core/isa/
mod.rs
