Expand description
The Bloqade Lanes [Instruction] enum and its fixed encoding width.
The instruction set is defined once as a #[derive(Instruction, Parse)]
enum; vihaco’s derive macros generate the binary codec
([vihaco::instruction::WriteBytes] / FromBytes)
and the text (.sst) parser ([vihaco_parser_core::Parse]). See the
super module docs for the design rationale (CPU-op reuse via
Cpu, native byte layout).
Enums§
- Instruction
- The Bloqade Lanes instruction set, defined on the vihaco framework.
Constants§
- INSTRUCTION_
WIDTH - Fixed width, in bytes, of every encoded instruction word: 1 opcode byte
plus a payload up to the nested [
vihaco_cpu::Instruction] word (16 bytes), zero-padded. Decoding consumes exactly this many bytes per instruction, so a flat program decodes without desync.