Module isa 

Vihaco-backed instruction set (ISA) for the Bloqade Lanes bytecode.

This is the bytecode instruction set, built on the [vihaco] virtual-ISA framework (the migration off the original hand-rolled format), per https://github.com/QuEraComputing/bloqade-lanes/issues/769.

The instruction set is defined once as a #[derive(Instruction, Parse)] enum; vihaco’s derive macros then generate:

• binary encode/decode ([vihaco::instruction::WriteBytes] / [vihaco::instruction::FromBytes]) — a 1-byte opcode followed by a little-endian payload, zero-padded to a fixed INSTRUCTION_WIDTH-byte word, so a program is simply N concatenated words;
• a text (.sst) parser ([vihaco_parser_core::Parse]).

This adopts vihaco’s native byte layout (the issue #769 decision); it is intentionally not compatible with the original BLQD container that the hand-rolled bytecode used.

CPU ops are reused from vihaco-cpu

Rather than re-defining stack/const opcodes, the Instruction::Cpu variant nests the entire [vihaco_cpu::Instruction] set (a stack machine with const.<type>, dup, halt, arithmetic, …), with parsing #[delegate]d to vihaco-cpu’s own parser and printing via its Display. Three stack ops stay lanes-native because vihaco-cpu can’t round-trip them through text:

• pop, swap — vihaco-cpu has no such opcodes;
• return — vihaco-cpu’s Return is parser-deferred to an orchestrator (ret does not parse standalone), and lanes needs a terminator that round-trips.

Consequence: CPU text syntax is now vihaco-cpu’s (const.i64 42, const.f64 1.5, dup, halt), not the legacy const_int / const_float.

Re-exports

pub use def::INSTRUCTION_WIDTH;

pub use def::Instruction;

pub use program::LanesInfo;

pub use program::Program;

pub use program::from_code;

pub use text::parse_text;

pub use text::to_text;

Modules

def

The Bloqade Lanes [Instruction] enum and its fixed encoding width.

parse_helpers

Field-level #[parse_with] helpers for super::Instruction.

program

Flat program container for the vihaco-backed ISA.

text

Text (.sst) codec for the vihaco-backed ISA — vihaco ParsedModule grammar.

validate

Architecture-dependent validation for the vihaco-backed ISA.